Method of fabricating a semiconductor interconnect structure

ABSTRACT

The present invention is directed to a semiconductor interconnect structure comprised of a promoter layer defining openings and a metal layer having a portion elevated above the substrate assembly and a portion that fills the openings. The metal layer is in electrical contact with the substrate assembly through the portion of the metal layer that fills the openings. The portion of the metal layer that fills the openings supports the elevated portion of the metal layer. A method of fabricating a semiconductor interconnect structure is also provided. A resist layer is patterned on a substrate assembly to define openings. A metal layer is deposited on the resist layer and into the openings, and the resist layer is removed to form a gap between the metal layer and the underlying substrate assembly.

CROSS REFERENCE TO RELATED APPLICATIONS (Not Applicable) STATEMENTREGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0001] (Not Applicable)

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention is directed generally to semiconductorinterconnect layers exhibiting a low RC time delay, and, moreparticularly, to semiconductor interconnect layers made of a materialhaving a low resistivity that is surrounded by a material with a lowdielectric constant.

[0004] 2. Description of the Background

[0005] It is common in the semiconductor art to use layers of metal,polysilicon, or another conductor to conduct current between varioussemiconductor devices that form integrated circuits. The layers ofconductor are connected to each other by means of vias and are connectedto other materials by means of contacts.

[0006] When a metal is used to form the interconnect layers ofconductors, the metal is usually deposited on the semiconductor bysputtering, chemical vapor deposition (CVD), or evaporation. The CVDprocess forms a non-volatile solid film on a substrate by the reactionof vapor phase chemicals that contain the desired constituents. Themetals that are commonly used for the interconnect layers are aluminumand its alloys. The metal layers are typically deposited over dielectricmaterials, such as silicon dioxide. Thus, parallel plate capacitiveeffects are observed due to this structure. The capacitance for a layercan be represented as: $\begin{matrix}{C = \frac{\varepsilon_{0}\varepsilon_{ins}A}{D}} & (1)\end{matrix}$

[0007] where:

[0008] D=SiO₂ thickness

[0009] A=Area of plates

[0010] ε₀=Permittivity of free space

[0011] ε_(ins)=Permittivity of SiO₂

[0012] This capacitance increases as the density of the integratedcircuits increases. Also, the line resistance due to the metal layersincreases as the density of the integrated circuits increases. Theresistance of a sheet of conducting material is given as:$\begin{matrix}{R_{s} = \frac{p\quad l}{t\quad W}} & (2)\end{matrix}$

[0013] where:

[0014] p=Material resistivity

[0015] t=Material thickness

[0016] L=Material length

[0017] w=Material width

[0018] Thus, the time delay caused by the product of the line resistanceand the capacitance becomes critical.

[0019]FIG. 1 shows a cross sectional view of a typical semiconductordevice (a transistor) in simplified form. A Local Oxidation of Silicon(LOCOS) process is performed on a substrate layer 10 to create a gateoxide region 12 separated by field oxide regions 13. A polysilicon layer14 is then deposited, typically to form the gate structure of thetransistor, and a spacer 15 is fabricated around the remainder of layer14. Impurities are diffused into the substrate layer 10 to formdiffusion areas 16, which typically form the drain and source structuresof the transistor. A layer of silicon dioxide 18 is grown and thecontact and via areas are removed by etching. A silicide or metal layer20 is formed on the diffusion areas 16, which typically provide areasfor interconnection with the drain and source structures of thetransistor. A first layer of metal 22, typically aluminum or an alloy ofaluminum, is then deposited and areas are removed to form the requiredinterconnection pattern. Alternatively, metal contact plugs may beformed in the contact and via area formed in layer 18. Subsequent layersof silicon dioxide and metal may be grown and deposited, respectively,depending on the interconnection pattern required for the integratedcircuit.

[0020] An attempt to reduce the capacitance associated with interconnectlayers deposited on dielectric materials is shown in Togo, et al., “AGate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance inMOSFETs”, 199G Symposium on VLSI Technology Digest of Technical Papers,pp. 38-39. Togo, et al. outlines a transistor structure in which thesidewalls of the gate structure are surrounded by an air gap. A siliconnitride sidewall is first fabricated that surrounds the gate. A layer ofsilicon dioxide is formed around the silicon nitride sidewall. Thesilicon nitride sidewall is removed by a wet etching process to form anair gap between the gate structure and the silicon dioxide.

[0021] Another attempt to reduce the capacitance associated withinterconnect layers deposited on silicon is shown in Anand, et al.,“NURA: A Feasible, Gas-Dielectric Interconnect Process”, 1996 Symposiumon VLSI Technology Digest of Technical Papers, pp. 82-83. Anand, et al.outlines a metal interconnect structure in which layers of a gas areformed between thin layers of silicon dioxide. The thin layers ofsilicon dioxide have metal interconnect layers deposited on them. Theprocess begins when layers of carbon are formed on a surface andtrenches are formed for future interconnections. An interconnect metallayer is formed in the carbon trenches and a thin layer of silicondioxide is sputter-deposited. Oxygen is then furnace ashed into thecarbon layer through diffusion and the oxygen reacts with the carbon toform carbon dioxide. This process is repeated to form the interconnectstructure of the device under fabrication.

[0022] Although Togo, et al. Claims to reduce the capacitance associatedwith the interconnect layers by reducing the dielectric constant of thematerials between the interconnect layers, Togo, et al. only provides alow dielectric material (air) around the gate contact of a transistor.Also, Togo, et al. does not disclose an interconnect structure that hasreduced resistivity.

[0023] Likewise, even though Anand, et al. Claims to reduce thecapacitance associated with the interconnect layers by reducing thedielectric constant of the materials between the interconnect layers,Anand, et al. adds complexity to the semiconductor fabrication processbecause carbon is used in the process, which is not typically used inthe manufacture of semiconductor devices. The method of Anand, et al.does not disclose an interconnect structure that has reducedresistivity.

[0024] Thus, the need exists for a semiconductor interconnect structurewith reduced capacitance and reduced resistivity, thereby decreasing theRC time delay associated with the interconnect layers. The need alsoexists for a method of fabricating such a structure using standardfabrication steps in conjunction with commercially available processingequipment.

SUMMARY OF THE INVENTION

[0025] The present invention is directed generally to a semiconductorinterconnect structure and a method of making the same. Layers ofphotoresist are formed between conductive layers and the photoresist isremoved by, for example, ashing in oxygen plasma. When the photoresistlayers are removed, the conductive layers are surrounded by air, whichhas a dielectric constant of 1. The conductive layers are preferablycomprised of copper.

[0026] The present invention represents significant advantages over theprior art. Because the air spaces between the conductive interconnectlayers are formed by removing layers of photoresist, no extra materialneed be introduced into the semiconductor manufacturing process. Also,because the conductive interconnect layers are surrounded by air, theplate capacitance of the interconnect structure is reduced. Furthermore,because a low resistive material such as copper is used for theconductive interconnect layers, the resistance associated with theinterconnect structure is reduced. Using copper as the material for theinterconnect layers has the further advantage that the layers may beelectroplated or electroless plated at low temperatures. Thoseadvantages and benefits of the present invention, and others, willbecome apparent from the Detailed Description of the Inventionhereinbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures wherein:

[0028]FIG. 1 is a cross-sectional view of a typical prior artsemiconductor device;

[0029]FIG. 2 is a cross-sectional view of a substrate assembly on whicha layer of photoresist has been deposited, masked, hardened, and etched;

[0030]FIG. 3 is a cross-sectional view of the substrate assembly of FIG.2 on which a promoter layer has been deposited on the etched photoresistlayer;

[0031]FIG. 4 is a cross-sectional view of the substrate assembly of FIG.3 on which a metal layer has been deposited on the promoter layer;

[0032]FIG. 5 is a cross-sectional view of the substrate assembly of FIG.4 following removal of excess metal from the metal layer to form metalplugs;

[0033]FIG. 6 is a cross-sectional view of the substrate assembly of FIG.5 on which a photoresist layer has been deposited, masked, hardened, andetched on the promoter layer and metal plugs;

[0034]FIG. 7 is a cross-sectional view of the substrate assembly of FIG.6 on which a promoter layer and a first metal layer have been depositedon the etched photoresist layer;

[0035]FIG. 8 is a cross-sectional view of the substrate assembly of FIG.7 following the removal of excess metal from the first metal layer;

[0036]FIG. 9 is a cross sectional view of the substrate assembly of FIG.8 following the addition of a photoresist layer, a bilayer adhesionpromoter layer, a metal plug, and a second metal layer onto the etchedphotoresist layer and the first metal layer;

[0037]FIG. 10 is a cross-sectional view of the substrate assembly ofFIG. 9 following the removal of the photoresist layers to form gapsbetween the promoter layers and the underlying substrate assembly; and

[0038]FIG. 11 illustrates a semiconductor device in which the presentinvention may be used.

DETAILED DESCRIPTION OF THE INVENTION

[0039] It is to be understood that the figures have been simplified toillustrate only those aspects of semiconductor topography which arerelevant, and some of the dimensions have been exaggerated to convey aclear understanding of the present invention, while eliminating, for thepurposes of clarity, some elements normally found on a semiconductor.Those of ordinary skill in the art will recognize that other elementsand process steps are required to produce an operational semiconductor.However, because such elements and process steps are well known in theart, and because they do not further aid in the understanding of thepresent invention, a discussion of such elements is not provided herein.

[0040]FIG. 2 shows a cross-section of a substrate assembly 30 at anearly stage in the fabrication process of the present invention. Thesubstrate assembly 30 includes a substrate layer 32, which is the lowestlayer of semiconductor material on a wafer, and additional layers orstructures formed thereon. A LOCOS process is performed to provide alayer of gate oxide 33 separated by field oxide regions 34. Apolysilicon layer 36 is deposited and etched to provide a contact area,typically for the gate terminal of a transistor. A spacer 37 may beformed along the layer 36 using conventional techniques. Impurities arediffused into the substrate 34 through suitable masks to form diffusionareas 38. The diffusion areas 38 give rise to depletion regions thatessentially isolate the source and drain terminals of the transistorfrom one another by two diodes. Silicide layers 40 are formed on thediffusion areas 38. The silicide layers 40 are formed by depositing arefractory metal such as titanium, platinum, palladium, cobalt, ortungsten on polysilicon. The metal/silicon alloy is then sintered toform the silicide layers 40.

[0041] After the silicide layers 40 are formed, the substrate assembly30 is then ready for metallization. A layer of photoresist 42 isdeposited on the substrate assembly 30 and is masked, hardened, andetched to define openings 43 for contact plugs. The photoresist layer 42is hardened by baking the substrate assembly 30 at a temperaturetypically below 1000 C.

[0042]FIG. 3 shows the substrate assembly 30 of FIG. 2 after a bilayeradhesion promoter layer 44 is deposited by, for example, sputtering ontothe surface of the etched photoresist layer 42. Ionized sputtering ispreferred to provide effective coverage of the sidewalls of deepopenings. A chemical vapor deposition (CVD) process may also be used todeposit the bilayer adhesion promotor layer 44. The bilayer adhesionpromoter layer 44 can be, among other substances, titanium/copper,chromium/copper, titanium nitride/copper, or tantalum/copper.

[0043] As shown in FIG. 4, a metal layer 46 is formed by, for example,plating on the bilayer adhesion promoter layer 44. The metal layer 46 ispreferably copper, which can be electroplated or electroless plated onthe substrate assembly 30 at a process temperature around 30° C. Themetal layer 46 may also be deposited using a CVD process. The excessmetal from the metal layer 46 and the excess bilayer adhesion promoterlayer 44 are removed through mechanical abrasion, for example, bychemical mechanical polishing, to form metal plugs 48, as shown in FIG.5. The substrate assembly 30 is planar after the removal of the excessmetal and the remaining portions of the bilayer adhesion promoter layer44 define receptacles 45, in which the metal plugs 48 are located.

[0044] Another photoresist layer 50 is deposited onto the bilayeradhesion promoter layer 44 and the metal plugs 48 as shown in FIG. 6.The photoresist layer 50 is masked, hardened, and etched to defineopenings 51 for a metal layer which is aligned with the plugs 48. FIG. 7shows a bilayer adhesion promoter layer 52 deposited on the etchedphotoresist layer 50 and the metal plugs 48 and a first metal layer 54plated on the bilayer adhesion promoter layer 52. A portion of the metalfills the openings 51 forming contacts 53. Excess metal from the firstmetal layer 54 and excess bilayer adhesion promoter layer 52 are removedby mechanical abrasion, as shown in FIG. 8. Thus, the first metal layer54 has contacts 53 and the resulting substrate assembly is planar.

[0045]FIG. 9 illustrates the substrate assembly 30 of FIG. 8 afterphotoresist layer 62 is deposited, hardened and etched, bilayer adhesionpromoter layer 64 is deposited, and a metal layer is deposited onto thesubstrate assembly 30. The substrate assembly 30 in FIG. 9 has beenmechanically polished to remove the excess metal and the remainingportions of the bilayer adhesion promoter layer 64 to form metal plug 66in receptacle 68. A second metal layer 70 has been deposited on thesubstrate assembly 30 to form contact 72. Multiple layers of metal canbe built up by adding layers of bilayer adhesion promoter, photoresist,and metal.

[0046]FIG. 10 shows a resulting substrate assembly 30 of FIG. 9 with thefirst metal layer 54 and the second metal layer 70 formed. Thephotoresist layers 42, 50 and 62 are removed by, for example, ashing inoxygen plasma to form air gaps 56. The metal layers 54 and 70 aresupported by columns 60 and 74 formed by the combination of the metalplugs 48 and 66 and the contacts 53 and 72. The air gaps 56 have adielectric constant of 1, thereby reducing the capacitance of theresulting structure. By selecting appropriate metal conductors whichhave a low resistance, the RC time constant of the resulting structureis reduced.

[0047] The present invention also contemplates a method by which theabove-described semiconductor interconnect structure is fabricated usingtypical fabrication steps, materials, and machines. The method, in itsbroadest form, is comprised of the steps of depositing a layer ofphotoresist on a substrate assembly. The photoresist is etched to formopenings. A metal layer is formed on the photoresist layer so as to fillthe openings formed in the photoresist layer. Thereafter, thephotoresist layer is removed by, for example, ashing. The metal layer isthus supported by the metal which filled the openings formed in thephotoresist.

[0048] The method of the present invention may be modified by, forexample, depositing a promoter layer prior to forming the metal layer.Conventional techniques may be used for the “depositing” and “forming”steps such as sputtering and electroplating. A wide variety of metalsand promoters may be used in the process.

[0049]FIG. 11 illustrates a semiconductor device 58 in which the presentinvention may be employed. The semiconductor device 58 may be any typeof solid state device, such as a memory device.

[0050] While the present invention has been described in conjunctionwith preferred embodiments thereof, many modifications and variationswill be apparent to those of ordinary skill in the art. The foregoingdescription and the following claims are intended to cover all suchmodifications and variations.

What is claimed is:
 1. A method of fabricating a semiconductor interconnect structure, comprising the steps of: forming a patterned resist layer on a substrate assembly to define openings; depositing a metal layer on said resist layer and into said openings; and removing said resist layer to form a gap between said metal layer and said underlying substrate assembly.
 2. The method of claim 1 further comprising the step of depositing a promoter layer prior to said step of depositing a metal layer.
 3. The method of claim 2 wherein said step of depositing a promoter layer includes the step of ionized sputtering said promoter layer.
 4. The method of claim 2 wherein said step of depositing a metal layer includes the step of chemical vapor depositing said promoter layer.
 5. The method of claim 1 wherein said step of depositing a metal layer includes the step of electroplating copper.
 6. The method of claim 1 wherein said step of depositing a metal layer includes the step of electroless plating of copper.
 7. The method of claim 1 wherein said step of depositing a metal layer includes the step of chemical vapor depositing copper.
 8. The method of claim 1 wherein said step of removing said resist layer includes the step of ashing a plasma into said substrate assembly.
 9. A method of fabricating a semiconductor interconnect structure, comprising the steps of: depositing a first photoresist layer on a substrate assembly; removing certain of said first photoresist layer to form a first set of openings therein; depositing a first metal layer on said first photoresist layer and into said first set of openings; removing metal from said metal layer so as to leave metal plugs deposited into said first set of openings; depositing a second photoresist layer on said first photoresist layer and said metal plugs; removing certain of said second photoresist layer to form a second set of openings therein, said second set of openings aligned with said metal plugs; depositing a second metal layer on said second photoresist layer and into said second set of openings; and removing said first and second photoresist layers such that said second metal layer is supported by said metal plugs and said metal deposited into said second set of openings.
 10. The method of claim 9 further comprising the step of depositing a first promoter layer prior to said step of depositing a first metal layer.
 11. The method of claim 10 further comprising the step of depositing a second promoter layer prior to said step of depositing a second metal layer.
 12. The method of claim 10 wherein said step of depositing a first promoter layer includes the step of ionized sputtering said first promoter layer.
 13. The method of claim 10 wherein said step of depositing a first promoter layer includes the step of chemical vapor depositing said first promoter layer.
 14. The method of claim 11 wherein said step of depositing a second promoter layer includes the step of ionized sputtering said second promoter layer.
 15. The method of claim 11 wherein said step of depositing a second promoter layer includes the step of chemical vapor depositing said second promoter layer.
 16. The method of claim 9 wherein said step of depositing a first metal layer includes the step of electroplating copper.
 17. The method of claim 9 wherein said step of depositing a first metal layer includes the step of electroless plating copper.
 18. The method of claim 9 wherein said step of depositing a first metal layer includes the step of chemical vapor depositing copper.
 19. The method of claim 9 wherein said step of depositing a second metal layer includes the step of electroplating copper.
 20. The method of claim 9 wherein said step of depositing a second metal layer includes the step of electroless plating copper.
 21. The method of claim 9 wherein said step of depositing a second metal layer includes the step of chemical vapor depositing copper.
 22. The method of claim 9 wherein said step of removing said first and second photoresist layers includes the step of ashing oxygen plasma into said substrate assembly.
 23. A semiconductor interconnect structure for a substrate assembly, comprising: a promoter layer defining openings; and a metal layer having a portion elevated above said substrate assembly and a portion filling said openings such that said metal layer is in electrical contact with the substrate assembly through said metal filling said openings which metal supports said elevated portion.
 24. The semiconductor interconnect structure of claim 23 wherein said metal layer is comprised of copper.
 25. The semiconductor interconnect structure of claim 23 wherein said promoter layer is comprised of titanium and copper.
 26. The semiconductor interconnect structure of claim 23 wherein said promoter layer is comprised of chrominium and copper.
 27. The semiconductor interconnect structure of claim 23 wherein said promoter layer is comprised of titanium nitride and copper.
 28. The semiconductor interconnect structure of claim 23 wherein said promoter layer is comprised of tantalum and copper.
 29. A semiconductor interconnect structure for a substrate assembly, comprising: a first promoter layer defining a plurality of receptacles; a plurality of metal plugs formed in said plurality of receptacles; a second promoter layer defining a plurality of openings above said metal plugs; and a metal layer having a portion elevated above said substrate assembly and a portion filling said plurality of openings such that said metal layer is in electrical contact with the substrate assembly, said metal filling said plurality of openings and said plurality of metal plugs supporting said elevated portion of said metal layer.
 30. The semiconductor interconnect structure of claim 29 wherein said metal plugs and said metal layer are comprised of copper.
 31. The semiconductor interconnect structure of claim 29 wherein said first promoter layer and said second promoter layer are comprised of titanium and copper.
 32. The semiconductor interconnect structure of claim 29 wherein said first promoter layer and said second promoter layer are comprised of chromium and copper.
 33. The semiconductor interconnect structure of claim 29 wherein said first promoter layer and said second promoter layer are comprised of titanium nitride and copper.
 34. The semiconductor interconnect structure of claim 29 wherein said first promoter layer and said second promoter layer are comprised of tantalum and copper.
 35. A semiconductor device, comprising: a substrate assembly; and at least one interconnect structure, said interconnect structure comprising: a promoter layer defining receptacles; and a metal layer having a portion elevated above said substrate assembly and a portion filling said openings such that said metal layer is in electrical contact with the substrate assembly through said metal filling said openings which metal supports said elevated portion.
 36. A semiconductor device, comprising: a substrate assembly; and at least one interconnect structure, said interconnect structure comprising: a first promoter layer defining a plurality of receptacles; a plurality of metal plugs formed in said plurality of receptacles; a second promoter layer defining a plurality of openings above said metal plugs; and a metal layer having a portion elevated above said substrate assembly and a portion filling said plurality of openings such that said metal layer is in electrical contact with the substrate assembly, said metal filling said plurality of openings and said plurality of metal plugs supporting said elevated portion of said metal layer. 